One of the continuing goals of the semiconductor industry is the production of smaller microelectronic devices and denser integrated circuits. In order to produce microelectronic devices having dimensions which are small enough to meet the requirements of Ultra Large Scale Integration (ULSI), both the lateral and vertical dimensions of the microelectronic devices in a semiconductor substrate must be reduced. In particular, as device sizes shrink, there is a need to form shallow doped regions of a predetermined conductivity at the face of the semiconductor substrate. These shallow regions, currently less than about fifteen hundred .ANG.ngstroms in depth, can be used to form p-n junctions with the semiconductor substrate or other regions of the semiconductor substrate. Furthermore, as the dimensions of microelectronic devices shrink, the contact areas decrease resulting in increased contact resistance. For example, a decrease in device size by a factor of 5 will increase the contact resistance by a factor of 25 unless the contact resistivity can be lowered. The increased resistance reduces the overall performance of the microelectronic device and, in particular, the increased resistance reduces the speed at which the device can operate. Accordingly, there is also a need to form low resistance contacts to these shallow doped regions.
The use of a silicon-germanium alloy as a diffusion source for forming shallow doped regions in a semiconductor substrate without ion implantation is disclosed in U.S. Pat. No. 5,242,847 to Ozturk et al. entitled "Selective Deposition of Doped Silicon-Germanium Alloy On Semiconductor Substrate." In this patent, a layer of a doped silicon-germanium alloy is formed on a defined area of a face of a semiconductor substrate. The substrate is then heated to diffuse at least some of the dopant from the silicon-germanium alloy layer into the substrate. A metal layer is then deposited on the alloy layer and heated so as to react with the alloy thereby forming a germanosilicide contact. The alloy layer is preferably consumed by the germanosilicide. The siticon-germanium alloy can be deposited selectively at 600.degree. C. which is below the temperature at which dopant diffusion occurs in silicon. The alloy also has a melting point of 937.degree. C. that is high when compared to the melting point of pure germanium. Accordingly, the alloy is not destroyed during a subsequent anneal. Furthermore, the alloy has a higher growth rate and better selectivity when compared to silicon alone.
The use of germanium containing contacts is disclosed in U.S. Pat. No. 5,089,872 to Ozturk et al. entitled "Selective Germanium Deposition On Silicon And Resulting Structures." In this patent, a germanium layer is selectively deposited on a portion of a silicon substrate such as a source or drain of a field effect transistor. The selective deposition is achieved by exposing the substrate to a germanium containing gas at a temperature high enough that the germanium will deposit on silicon but low enough that the germanium will not deposit on silicon dioxide. Dopant atoms can be added to the deposited germanium and diffused into the silicon surface to form doped silicon portions. In addition, metal can be deposited on the germanium and annealed to form a germanide compound. The amount of metal used is selected to produce a sufficient amount of germanide to produce a desired level of resistivity in the resulting contact.
The use of a germanium layer as a sacrificial barrier between reactive metal and silicon in a silicided contact process is disclosed in the reference by Grider et al. entitled "Low-Resistivity Contacts to Silicon Using Selective RTCVD of Germanium", SPIE, Vol. 1393, Rapid Thermal and Related Processing Techniques, pp. 229-239, 1990. This use of germanium has the advantages of the high selectivity and low temperature of germanium deposition, low temperature for dopant activation, and the possibility for lower resistivity contacts to the underlying junctions by virtue of germanium's narrow bandgap.
The use of contacts including a germaniumsilicon composite or germanium in a single crystal structure with the underlying silicon is disclosed in U.S. Pat. No. 4,983,536 to Bulat et al. entitled "Method of Fabricating Junction Field Effect Transistor." The bandgap between the metalization and the underlying silicon is reduced by the presence of the germanium. Thus, the contact resistance is decreased. The performance of an evaporated amorphous germanium film is discussed in the reference by Norde et al. entitled "Behavior of Amorphous Ge Contacts to Monocrystalline Silicon," Vacuum, Vol. 27, No. 3, pp. 201-208.
An interconnect structure comprising a germanium-silicon binary alloy is disclosed in U.S. Pat. No. 4,442,449 to Lehrer et al. entitled "Binary Germanium-Silicon Interconnect and Electrode Structure for Intergrated Circuits." In this patent, a germanium-silicon alloy is deposited on a semiconductor wafer. The alloy can be oxidized, selectively removed and doped with impurities to provide a conductive lead pattern of a desired shape on the surface of the wafer.
Notwithstanding the above described contact and interconnect forming methods, there continues to be a need for a method of forming shallow doped regions at the face of a semiconductor substrate which eliminates damage to the substrate resulting from ion implantation. There is also a need for a method to form low resistance contacts at these doped regions without consuming the substrate surface. Preferably, a single method should be used to form both the doped regions and the low resistance contacts, and this method is most preferably compatible with existing microelectronic manufacturing processes.